64 lines
3.0 KiB
C
64 lines
3.0 KiB
C
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//
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// Gertboard test suite
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//
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// spi header file
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//
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// Copyright (C) Gert Jan van Loo & Myra VanInwegen 2012
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// No rights reserved
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// You may treat this program as if it was in the public domain
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// SPI macros and constants. There are lots!
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//
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#define SPI0_CNTLSTAT *(spi0 + 0)
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#define SPI0_FIFO *(spi0 + 1)
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#define SPI0_CLKSPEED *(spi0 + 2)
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// SPI0_CNTLSTAT register bits
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#define SPI0_CS_CS2ACTHIGH 0x00800000 // CS2 active high
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#define SPI0_CS_CS1ACTHIGH 0x00400000 // CS1 active high
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#define SPI0_CS_CS0ACTHIGH 0x00200000 // CS0 active high
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#define SPI0_CS_RXFIFOFULL 0x00100000 // Receive FIFO full
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#define SPI0_CS_RXFIFO3_4 0x00080000 // Receive FIFO 3/4 full
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#define SPI0_CS_TXFIFOSPCE 0x00040000 // Transmit FIFO has space
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#define SPI0_CS_RXFIFODATA 0x00020000 // Receive FIFO has data
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#define SPI0_CS_DONE 0x00010000 // SPI transfer done. WRT to CLR!
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#define SPI0_CS_MOSI_INPUT 0x00001000 // MOSI is input, read from MOSI (BI-dir mode)
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#define SPI0_CS_DEASRT_CS 0x00000800 // De-assert CS at end
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#define SPI0_CS_RX_IRQ 0x00000400 // Receive irq enable
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#define SPI0_CS_DONE_IRQ 0x00000200 // irq when done
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#define SPI0_CS_DMA_ENABLE 0x00000100 // Run in DMA mode
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#define SPI0_CS_ACTIVATE 0x00000080 // Activate: be high before starting
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#define SPI0_CS_CS_POLARIT 0x00000040 // Chip selects active high
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#define SPI0_CS_CLRTXFIFO 0x00000020 // Clear TX FIFO (auto clear bit)
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#define SPI0_CS_CLRRXFIFO 0x00000010 // Clear RX FIFO (auto clear bit)
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#define SPI0_CS_CLRFIFOS 0x00000030 // Clear BOTH FIFOs (auto clear bit)
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#define SPI0_CS_CLK_IDLHI 0x00000008 // Clock pin is high when idle
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#define SPI0_CS_CLKTRANS 0x00000004 // 0=first clock in middle of data bit
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// 1=first clock at begin of data bit
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#define SPI0_CS_CHIPSEL0 0x00000000 // Use chip select 0
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#define SPI0_CS_CHIPSEL1 0x00000001 // Use chip select 1
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#define SPI0_CS_CHIPSEL2 0x00000002 // No chip select (e.g. use GPIO pin)
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#define SPI0_CS_CHIPSELN 0x00000003 // No chip select (e.g. use GPIO pin)
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#define SPI0_CS_CLRALL (SPI0_CS_CLRFIFOS|SPI0_CS_DONE)
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// SPI functions
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void setup_spi(void);
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int read_adc(int);
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void write_dac(int, int);
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